1. Field of the Invention
The present invention relates to a solid-state imaging apparatus, a method of manufacturing the solid-state imaging apparatus, and an electronic apparatus used for, for example, a camera including the solid-state imaging apparatus.
2. Description of the Related Art
An example of a solid-state imaging apparatus is a CMOS solid-state imaging apparatus. Because CMOS solid-state imaging apparatuses have a low power-supply voltage and have low consumption of power, they are used for digital still cameras, digital video cameras, various portable terminal devices such as mobile phones with camera, printers, and the like.
CMOS solid-state imaging apparatuses are configured to include a pixel area in which a plurality of pixels constituted by a photodiode that is a photoelectric conversion unit and a plurality of pixel transistors are two-dimensionally arranged in a regular manner, and a peripheral circuit unit arranged in the area surrounding the pixel area. Peripheral circuit units include a column circuit (vertical driving unit) for propagating a signal in the column direction, and a horizontal circuit (horizontal transfer unit) for transmitting signals of each column, which are propagated by the column circuit in sequence to an output circuit, and the like. An example of the plurality of pixel transistors is a configuration using 3 transistors, namely, a transfer transistor, a reset transistor, and an amplification transistor, or using 4 transistors in which a selection transistor is added thereto.
In CMOS solid-state imaging apparatuses, when a photodiode is irradiated with an amount of light to such an extent that electric charge that is photoelectrically converted by a photodiode overflows, it is necessary to discharge the overflowing electric charge to an overflow drain. An example of an overflow mechanism is a vertical overflow structure in which a power-supply potential is set on the back surface of a semiconductor substrate, and the substrate back surface is set as an overflow drain, so that the overflowing charge is discharged toward the substrate back surface side. Furthermore, an example of a overflow mechanism is a horizontal overflow structure in which a floating diffusion unit or another power-supply potential is set as an overflow drain, so that electric charge that is overflowing from a photodiode is discharged in the horizontal direction.
FIG. 12 schematically shows the main portion of a CMOS solid-state imaging apparatus including a vertical overflow structure. In a CMOS solid-state imaging apparatus 111, a p-type semiconductor well area 113 formed on an n-type semiconductor substrate (not shown) is formed with a pixel 115 that includes a plurality of pixel transistors including a photodiode PD and a transfer transistor Tr1 that are divided by an element isolation area 114. The photodiode PD is configured to include a low concentration n-type semiconductor area 116, a high concentration n-type charge storage area 117 on the surface side thereof, and a p-type semiconductor area 118 on the surface of the n-type charge storage area 117. The p-type semiconductor area 118 has a comparatively high concentration and also serves to suppress dark current. A transfer gate electrode 121 is formed between the photodiode PD and an n-type floating diffusion unit FD with a gate insulating film 119 in between, thereby forming the transfer transistor Tr1. Reference numeral 122 denotes a side wall formed on the side surface of the transfer gate electrode 121.
In the CMOS solid-state imaging apparatus 111, a substrate potential (power-supply potential) is applied to the back surface of a semiconductor substrate, and the substrate back surface operates as an overflow drain and a p-type semiconductor area provided below a photodiode PD operates as an overflow barrier. Overflowing charge is discharged in a vertical direction on the back surface side of the substrate, as indicated by an arrow 123.
FIG. 13 schematically shows the main portion of a CMOS solid-state imaging apparatus having a horizontal overflow structure. In this CMOS solid-state imaging apparatus 131, in a manner similar to that described above, a p-type semiconductor well area 113 forms a pixel 115 that includes a plurality of pixel transistors including a photodiode PD and a transfer transistor Tr1 divided by the element isolation area 114. Components in FIG. 13 corresponding to those of FIG. 14 are designated with the same reference numerals, and repeated description thereof is omitted.
This CMOS solid-state imaging apparatus 131 is configured so that the floating diffusion unit FD serves as an overflow drain, and a channel potential below the transfer gate electrode 121 operates as an overflow barrier. Overflowing charge is discharged toward the floating diffusion unit side in the horizontal direction, as indicated by an arrow 133.
In the case of a CMOS solid-state imaging apparatus of a top surface irradiation type using an n-type semiconductor substrate, a vertical overflow structure can be adopted. In the vertical overflow structure, an overflow barrier is formed by ion-implanting a p-type impurity over the entire pixel area at a position deep within a substrate in the bottom part of the photodiode PD. This overflow barrier is determined by the dosage of a p-type impurity to be implanted, and the influence of manufacturing variations is small.
In comparison, in the case of a CMOS solid-state imaging apparatus of a back surface irradiation type or in the case of a CMOS solid-state imaging apparatus of a top surface irradiation type using a p-type semiconductor substrate, a device is necessary to set a power-supply potential on the substrate back surface. For this reason, usually, a horizontal overflow structure is formed. When a horizontal overflow structure is to be formed, an overflow path is formed in which a potential barrier below a transfer gate electrode is lowered, and electric charge leaked from the photodiode PD passes below the transfer gate electrode and flows into the floating diffusion unit FD. It is common practice that, at the same time, the floating diffusion unit FD be formed as an overflow drain.
In Japanese Unexamined Patent Application Publication Nos. 2006-49338, 2003-31785, 2007-158031, 2008-166607, 2008-205022, 2009-016810, and 2000-286405, related art of a CMOS solid-state imaging apparatus is disclosed. Japanese Unexamined Patent Application Publication No. 2006-49338 discloses a configuration in which a photodiode is extended to below a floating diffusion unit. Japanese Unexamined Patent Application Publication No. 2003-31785 discloses a configuration in which a CMOS solid-state imaging apparatus of a back surface irradiation type. Japanese Unexamined Patent Application Publication Nos. 2007-158031 and 2008-166607 disclose a configuration in which a side wall is formed on the side surface of a gate electrode in a pixel transistor of a CMOS solid-state imaging apparatus. Japanese Unexamined Patent Application Publication No. 2008-205022 discloses a configuration in which an element isolation area is formed in the surroundings of a floating diffusion unit in a CMOS solid-state imaging apparatus. Japanese Unexamined Patent Application Publication No. 2009-016810 discloses a configuration in which a pixel transistor of a CMOS solid-state imaging apparatus is separated in a diffusion layer or in an element isolation area of a shallow trench isolation (STI) structure. Japanese Unexamined Patent Application Publication No. 2000-286405 discloses a configuration in which an n-type semiconductor area is formed on the side of a photodiode of a gate electrode of a transfer transistor in a CMOS solid-state imaging apparatus.